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Presentation_ID
9
Front Panel CPU Complex
RSP Engine Architecture
4GB MEM
I/O FPGA
HDD
Mgt Eth
CF card
Console
NVRAM Boot Flash
EOBC/
Internal GE switch
Ether
Switch
Timing Domain
Clock
Time
FPGA
BITS
4G disk
Mgt Eth
Aux
Alarm
Switch fabric
Punt
FPGA
Arbitration
Crossbar
Fabric
ASIC
Crossbar
Fabric
ASIC
FIA
CPU
Arbiter
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