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Appendix A: Glossary Intel® Server Board SE7501WV2
Revision 1.0
Intel reference number C25653-001
170
Term Definition
MT Mega transfers or million transactions
Mux multiplexor
NIC Network Interface Card
NMI Non-maskable Interrupt
OEM Original equipment manufacturer
Ohm Unit of electrical resistance
P32-A 32-bit PCI Segment
P64-B Full Length 64/133 MHz PCI Segment
P64-C low-profile 64/133 MHz PCI Segment
P64H2 PCI 64bit Hub 2.0
PBGA Pin Ball Grid Array
POST Power-on Self Test
RAM Random Access Memory
RISC Reduced instruction set computing
ROM Read Only Memory
DDR Synchronous Dynamic RAM
SDR Sensor Data Record
SEL System event log
SM Server Management
SMI Server management interrupt. SMI is the highest priority nonmaskable interrupt.
TBD To Be Determined
UART Universal asynchronous receiver and transmitter
USB Universal Serial Bus
Word 16-bit quantity
- Server Board 1
- SE7501WV2 1
- Revision History 2
- Disclaimers 2
- Table of Contents 3
- Revision 1.0 10
- List of Figures 12
- List of Tables 13
- 1. Introduction 17
- 2.1 SE7501WV2 Feature Set 18
- Figure 1. Intel 20
- 3. Functional Architecture 21
- 3.1.2 Memory Subsystem 23
- Table 3. Memory Bank Labels 25
- J5F1 J5F2 J5F3 J6F1 J6F2 26
- 3.2 Intel 27
- E7501 Chipset 27
- 3.2.2 MCH North Bridge 28
- 3.2.3 P64H2 29
- 3.2.4 ICH3-S 30
- • General purpose I/O 31
- 3.3 Super I/O 32
- 3.3.2 Serial Ports 33
- 3.3.3 BIOS Flash 37
- 4.1.1 Main Memory 38
- 4.1.2 Memory Shadowing 38
- 4.2 I/O Map 39
- Register 40
- Device Bus Number Reserved 40
- 4.4 Hardware Initialization 41
- 4.6 PCI I/O Subsystem 44
- 4.7 Ultra320 SCSI 47
- 4.8 ATA-100 47
- 4.9 Video Controller 48
- Table 17. Video Modes 49
- 4.11 Interrupt Routing 50
- Table 20. Intel 52
- 5. Server Management 54
- • Chassis intrusion detect 55
- Table 21. BMC Pinout 55
- 5.2 System Reset Control 62
- 5.2.3 Soft Reset 63
- 5.5 Error Reporting 64
- Table 24. System Status LEDs 65
- 5.5.6 Temperature Sensors 70
- 6. BIOS 71
- 6.3 Memory 72
- 6.3.1 Memory Configuration 73
- 6.4 Processors 74
- 6.5.1 Resource Allocation 75
- 6.6 NVRAM API 76
- 6.10 Floppy Drives 77
- 6.12.1 IPMI 78
- 6.12.3 Wake Events 80
- 6.12.4 Front Panel Switches 80
- 6.13 Console Redirection 82
- 6.13.1 Operation 83
- 6.13.2 Keystroke Mappings 83
- 6.13.3 Limitations 86
- 6.15 Service Partition Boot 87
- 6.17.1 Quiet Boot 91
- 6.18.1 CMOS Reset 91
- 6.19 BIOS Updates 92
- 6.19.3 User Binary Area 93
- 6.19.4 BIOS Recovery Mode 93
- 6.20 BIOS and System Setup 95
- • Exit Menu 98
- Advanced Menu 100
- Revision 1.0 103
- 6.21 BIOS Security Features 109
- 6.22 Password Protection 110
- 6.31 Error Handling 112
- 6.33 PCI Bus Error 113
- 6.34 Processor Bus Error 113
- 6.32 SMI Handler 113
- 6.36 System Limit Error 114
- 6.37 Boot Event 114
- • Disable FRB2 timer 115
- 6.39 Boot Monitoring 116
- 6.40.1 Memory Error Events 118
- 6.40.2 PCI Error Events 120
- 6.40.3 FRB-2 Error Events 121
- 6.44 INT 15 Extensions 127
- 6.44.2 Intel ID String 128
- 6.44.3 Processor Information 129
- 6.44.5 IPMB Services 130
- Master Write IMB 130
- Mixed Processor Support 131
- 6.47 OEM Customization 132
- 6.48 User Binary 132
- 6.48.3 OEM Splash Screen 135
- 6.48.4 Localization 135
- 7.1 ACPI 136
- 8. SE7501WV2 Connectors 139
- 8.2 Memory Module Connector 140
- 8.3 Processor Socket 141
- 8.4.1 ICMB Header 143
- 8.4.2 OEM IPMB Header 143
- 8.6 Front Panel Connectors 146
- 8.6.2 VGA Connector 149
- 8.6.3 SCSI Connectors 149
- 8.6.4 NIC Connector 150
- 8.6.5 ATA RAID Connectors 151
- 8.6.6 USB Connector 152
- 8.6.7 Floppy Connector 153
- 8.6.8 Serial Port Connector 154
- 8.7 Miscellaneous Headers 155
- 9. Configuration Jumpers 156
- 10. General Specifications 158
- 10.3.1 Power Timing 159
- ADVARSEL! 165
- ADVARSEL 165
- VARNING 165
- VAROITUS 165
- 12.1 PCI Riser Cards 167
- Appendix A: Glossary 168
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