Cisco NPE-G2 - Network Processing Engine G2 Especificaciones descargar pdf (Pagina 10)

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Network Processing Engine and Network Services Engine Installation and Configuration

OL-4448-12

Chapter 6 NPE-G2 Overview

NPE-G2 Description and Overview

Note The Gigabit Ethernet interfaces on the NPE-G2 do not support the Inter-Switch Link (ISL) VLAN

encapsulation protocol. We recommend that customers use the IEEE 802.1Q VLAN encapsulation

protocol as an alternative. Where an application requires the use of ISL, this can be provided by the Fast

Ethernet or Gigabit Ethernet port adapters or I/O controllers.

System Management Functions

The NPE-G2 performs the following system management functions:

• Sending and receiving routing protocol updates

• Managing tables, caches, and buffers

• Monitoring interface and environmental status

• Providing Simple Network Management Protocol (SNMP) management through the console and

Telnet interface

• Accounting for and switching of data traffic

• Booting and reloading images

• Managing port adapters (including recognition and initialization during online insertion and

removal)

Terms and Acronyms

• Boot ROM—Read-only memory that stores the boot image for bringing up the Cisco IOS image.

• Cache—Memory with fast access and small capacity used to temporarily store recently accessed

data; found either incorporated into the processor or near it.

• CWDM— Coarse Wavelength-Division Multiplexing.

• DIMM— Dual In-line Memory Module.

• DDR SDRAM—double data rate synchronous dynamic random-access memory.

• Flash memory—Location where the basic boot image is stored.

• Instruction and data cache—Instructions to the processor, and data on which the instructions work.

• Integrated cache—Cache that is built into the processor; sometimes referred to as internal cache.

Cache memory physically located outside the processor is not integrated, and is sometimes referred

to as external cache.

• LDT bus—lightning data transport bus.

• NVRAM—nonvolatile random-access memory.

• OTP—one time programmable.

• Primary and secondary cache—Hierarchical cache memory storage based on the proximity of the

cache to the core of the processor. Primary cache is closest to the processor core and has the fastest

access. Secondary cache has slower access than primary cache.

• RAM—random-access memory.

• RISC—reduced instruction set computing.

• ROM—read-only memory.

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