
Cisco UCS C460 M2 High-Performance Rack-Mount Server
SUPPLEMENTAL MATERIAL
47
■ The DIMMs in any given pair must be identical.
■ Any DIMM installed in a memory riser corresponding to an empty CPU slot becomes
inaccessible.
■ For optimal performance, distribute DIMMs evenly across all installed CPUs and memory
buffers.
■ DIMMs within a subchannel are populated starting with the DIMMs farthest from the memory
buffer in a fill-farthest approach.
■ For example, the order that you should populate the four channels on a memory riser is as
follows (see also
Figure 9 on page 46):
— 1.Slots 1B and 1D (buffer 1, subchannel 1)
— 2.Slots 1A and 1C (buffer 1, subchannel 2)
— 3.Slots 2B and 2D (buffer 2, subchannel 1)
— 4.Slots 2A and 2C (buffer 2, subchannel 2
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